1. Technical Field
The present invention relates to a display data channel (DDC) communication module, and more particularly, to a DDC communication module adopting an inter-integrated circuit (I2C) communication protocol.
2. Background Art
A display data channel (DDC) communication module employing an inter-integrated circuit (I2C) is disclosed in U.S. Patent Publication No. 2003-0053172 lodged by the present applicant, entitled “Optical Communication Interface Module Connected to Electrical Communication Interface Module of I2C Communication Protocol”.
FIG. 1 is a timing diagram for explaining an I2C communication protocol.
Referring to FIG. 1, the I2C communication protocol is a protocol for performing serial communication using only two channels, that is a channel for a serial data signal SDA and a channel for a serial clock signal SCL, without a channel for a control signal, unlike a conventional serial communication protocol. According to the I2C communication protocol, whenever the serial clock signal SCL is a logic level ‘1’ (a high voltage level), the state of the serial data signal SDA is set.
A time t1 at which the serial data signal SDA falls from a logic level ‘1’ to a logic level ‘0’ (a low voltage level), while the serial clock signal SCL is a logic level ‘1’, is a starting time of a data packet. A time t14 at which the serial data signal SDA rises from a logic level ‘0’ to a logic level ‘1’, while the serial clock signal SCL is a logic level ‘1 (a high voltage level), is a terminating time of the data packet. Accordingly, in the period between t1 and t14 during which the data package is transmitted, the serial data signal SDA must not undergo logic transition while the corresponding serial clock signal SCL is a logic level ‘1’,
Data with a logic level ‘1’, data with a logic level ‘0’, data with a logic level ‘0’, data with a logic level ‘1’, data with a logic level ‘1’, and data with a logic level ‘0’ are sequentially transmitted or received, respectively, for the duration between t2 and t3, for the duration between t4 and t5, for the duration between t10 and t11, and for the duration between t12 and t13, in which the serial clock signal SCL is a logic level ‘1’.
FIG. 2 is a block diagram of a conventional digital visual interface (DVI) system DVI including a conventional DDC communication module DDC. Referring to FIG. 2, the conventional DVI system DVI includes: a host device 21 including a transition minimized differential signaling (TMDS) transmitter 211 and a graphics controller 212; TMDS communication lines TMDS; the conventional DDC communication module DDC; and a display device 22 including a TMDS receiver 221 and a serial electrically erasable and programmable read only memory EEPROM 222.
Extended display identification data (EDID), which contains information on the configuration and characteristics of the display device 22, is stored in the serial EEPROM 222 of the display device 22. According to rules of the video electronics standard association (VESA), an 8-bit access address of the serial EEPROM 222 of the display device 22 is “1010000x”. That is, the access address of the serial EEPROM 222 of the display device 22 is “10100001” in a read mode and “10100000” in a write mode.
The graphics controller 212 of the host device 21 reads the EDID stored in the serial EEPROM 222 of the display device 22 through I2C communication, and controls the operation of the TMDS transmitter 211 according to the read EDID. Accordingly, the TMDS transmitter 211 transmits image signals and clock signals to the TMDS receiver 221 via the TMDS communication lines TMDS.
The conventional DDC communication module DDC includes I2C interfaces EI1 and EI2, a serial data transmitting/receiving line TLD, a serial clock transmitting/receiving line TLC, a DDC power line between power terminals VD, and a connection state line between interface signal terminals HPD.
The I2C interfaces EI1 and EI2 connected to the serial data transmitting/receiving line TLD respectively transmit serial data from serial data output terminals SDA1OUT and SDA2OUT to the opposite I2C interfaces EI1 and EI2 via the serial data transmitting/receiving line TLD, and respectively input serial data from the serial data transmitting/receiving line TLD to serial data input terminals SDA1IN and SDA2IN.
Likewise, the I2C interfaces EI1 and EI2 connected to the serial clock transmitting/receiving line TLC respectively transmit clock signals from serial clock output terminals SCL1OUT and SCL2OUT to the opposite I2C interfaces EI1 and EI2 via the serial clock transmitting/receiving line TLC, and respectively input clock signals from the serial clock transmitting/receiving line TLC to serial clock input terminals SCL1IN and SCL2IN.
The graphics controller 212 supplies a direct current (DC) voltage via the DDC power line between the power terminals VD.
Since data with a logic level “1” is applied to the HPD while the display device 22 is operated, the graphics controller 212 of the host device 21 can determine whether the host device 21 is connected to the display device 22.
EDID defined by a standard published by VESA will now be explained with reference to FIG. 3. FIG. 3 is a block diagram of EDID defined by a standard of VESA.
Referring to FIG. 3, EDID includes 13 items I1 through I13.
In areas with addresses 000h through 007h, a header is stored as the first item I1.
In areas with addresses 008h through 011h, product identification (ID) is stored as the second item.
In areas with addresses 012h through 013h, the EDID structure version is stored as the third item I3.
In areas with addresses 014h through 018h, basic display parameters/characteristics are stored as the fourth item I4.
In areas with addresses 019h through 022h, color characteristics are stored as the fifth item I5.
In areas with addresses 023h through 025h, established timings are stored as the sixth item I6.
In areas with addresses 026h through 034h, standard timing ID is stored as the seventh item I7.
In areas with addresses 035h through 047h, a first detailed timing description or a monitor descriptor is stored as the eighth item I8.
In areas with addresses 048h through 059h, a second detailed timing description or a monitor descriptor is stored as the ninth item I9.
In areas with addresses 05Ah through 06Bh, a third detailed timing description or a monitor descriptor is stored as the tenth item I10.
In areas with addresses 06Ch through 07Dh, a fourth detailed timing description or a monitor descriptor is stored as the eleventh item I11.
In an area with an address 07Eh, an extension flag is stored as the twelfth item I12.
In an area with an address 07Fh, a checksum is stored as the thirteenth item I13.
However, the conventional DDC communication module DDC of FIG. 2 has problems of noise and signal attenuation in long range communication.